Investigating long-term reliability of the interconnects

Electronic equipment can be subjected to many different types of temperature shock over a wide range of frequencies and acceleration levels. Temperature cycling and temperature shock testing in electronics packaging are used to determine the resistance of electronic devices to sudden exposure to extreme changes of temperature.


The primary goals are to qualify the electronic interconnect options for real environment applications and to establish the reliability and failure mechanisms. The main approach at our lab is to investigate the changes in the microstructure and evaluate the possible deterioration in the mechanical strength after exposure of the electronic devices to the thermal cycles and shocks. Therefore, we couple the thermal cycling tests with microstructural analysis techniques, shear testings, and strive to establish a correlation between the two.

Parameters in this test are minimum temperature, maximum temperature, ramp rate, and the dwell time. The thermal stress profile typically starts at room temperature and ramps between the minimum and maximum temperatures. It also typically ramps at a desired ramp rate with a desired dwelling time for specific number of cycles.

Thermal stress can cause microstructural defects such as voids, cracks, delamination, board warpage, irregular plating, and poor hole fill.

The failure mechanisms caused by thermal stress are as follows:

  • Thermal fatigue initiated by nucleated defects and propagates to larger cracks,
  • Formation of cracks and degradation at the interfaces due to the difference in coefficient of thermal expansion (CTE).

 

Contact

Head of Research Group Microelectronics Packaging
Prof. Dr. Gordon Elger
Phone: +49 841 9348-2840
Room: A114
E-Mail: